Light generated from subjects nature have a unique wavelength value or range of wavelength values. Image sensors may capture an image of a subject using a semiconductor device that is responsive to external energy or light. The pixels of the image sensor may detect light generated from each subject and convert the detected light into electrical values.
Two types of semiconductor image sensors are charge coupled devices (CCD) based on a silicon semiconductor and CMOS image sensors based on sub-micron CMOS (Complementary Metal Oxide Semiconductor) technology.
A CCD may have a structure in which individual MOS capacitors are relatively close to each other and charge carriers may be stored in the capacitors and transferred. However, CCDs may often have limitations in that a complex driving methods may be required during operation, power consumption is relatively high, and the number of mask process steps during manufacturing is relatively large, which may create challenges in implementing a signal processing circuit in a CCD chip. To overcome these possible limitations in CCDs, CMOS image sensors has been further developed and studied.
CMOS image sensors may capture an image using a photodiode (PD) and a MOS transistor in each unit pixel of the CMOS image sensor to detect a signal in a switching manner. CMOS image sensors may have advantages of low production costs, low power consumption, and ease of integration into peripheral circuit chips compared to the CCD. Since CMOS image sensors may be produced by a CMOS manufacturing technique, a CMOS image sensor may be easily integrated into a peripheral system (e.g. amplification and signal processing systems), which may minimize production costs. CMOS image sensors may have high processing speeds and low power consumption, which can be about 1% of CCDs.
In CMOS image sensors, a photodiode may be formed in a semiconductor substrate through ion implantation. The size of the photodiode may be miniaturized to increase the number of pixels without increasing the size of the chip. In other words, a light receiving area of a CMOS image sensor may be designed to be relatively small. However, the stack height may not necessarily be reduced or minimized when the light receiving area is minimized in a CMOS image sensor. Accordingly, a backside-illuminated image sensor may be provided in which a structure or arrangement minimizing the step above the light receiving area and minimizes or substantially eliminates a light interference phenomenon due to metal wiring and/or metal connections.
In general, there are significant efforts to further reduce and/or minimize the size of micro-electronic systems. Chip scale packaging, flip chips, and multichip module may be applied to various electronic systems, such as mobile phones, hand-held computers, and chip cards. There is a general need and/or desire for complex devices having various functions, which often results in increases in the size of chip area to accommodate these various functions. However, chips with structures to accommodate various functions may have relatively low manufacturing yield when integrating a multi-function device, which may cause increases in costs due to complexity of device implementation, as well as other technical limitations. Wiring between sub systems may be limited in terms of performance, multi-functionality, and reliability of micro-electronic systems. These factors may be critical performance bottlenecks in IC generation. Accordingly, 3D integration technology may have significant potential to replace and/or supplement embedded SOC technology.
In 3D integration technology, a super contact may serve as a pad during packaging and a normal contact for general wiring connections may be formed together with a super contact on a single wafer.
A process for manufacturing a backside-illuminated image sensor according to the related art described below. First, a super contact hole may be formed to pass through an inter-layer dielectric layer formed on a semiconductor substrate. A buried insulating layer may serve as an etch stop point during back grinding and to reach near the end of the semiconductor substrate when forming the super contact hole. A shielding layer may be formed at the bottom and sidewalls of the super contact hole for shielding. The inter-layer dielectric layer may be formed of a silicon oxide film (SiO2). The shielding layer may be formed by depositing a silicon nitride film (SiN) and a silicon oxide film. The silicon nitride film may be used because desirable adhesion characteristics between the silicon oxide film and silicon. The shielding layer may also formed on the active region including the gate and the source and drain regions of a semiconductor structure.
A mask pattern may be formed such that the gate and the source and drain regions formed on the active region are exposed. A first normal contact hole and a second normal contact hole may be formed to pass through the exposed region of the shielding layer and the inter-layer dielectric layer on the active region and to respectively expose the gate and the source and drain regions.
A conductive material may be filled in the first normal contact hole, the second normal contact hole, and the super contact hole and planarization may be performed to form a first normal contact, a second normal contact, and a super contact. The super contact hole may be filled with tungsten (W). The backside of the semiconductor substrate may be grounded and etched until the buried insulating layer is exposed, thereby performing backside thinning on the backside of the semiconductor substrate.
When manufacturing a backside-illuminated image sensor of the related art, the normal contact hole may be formed after the super contact hole and the shielding layer are formed. When forming the super contact hole, the super contact hole may be formed to pass through the inter-layer dielectric layer. When forming the normal contact hole, the normal contact hole may be formed to pass through the inter-layer dielectric layer and the shielding layer.
However, from design requirement that require minimization of the weight and size of semiconductor devices, because the diameter of the normal contact hole is relatively small, it may be difficult to expose the inter-layer dielectric layer to the active region. Further, since the shielding layer is included, the depth may increase. Accordingly, in some implementations, the normal contact hole may not be properly formed, such that when a conductive material is filled into the normal contact hole to form the normal contact, defective filling has a significant likelihood of occurring.